1. Field of the Invention
The present invention relates to voltage regulator circuits. More particularly, the present invention relates to a trimming circuit and method for replica type voltage regulators.
2. Background Information
Voltage regulator circuits serve numerous purposes in integrated circuit devices. One such purpose can be as a regulated internal power supply voltage for sections of the integrated circuit device. A replica biased voltage regulator is a type of voltage regulator in which a voltage established in one portion of a circuit (e.g., one leg) is replicated, generally by larger-sized devices, to present a load (output) voltage. The load voltage is regulated by having it track the replica voltage as close as possible.
Conventional replica type voltage regulators use active (dynamic) line regulation and passive (static) load regulation. Such approaches can achieve a good high frequency transient response at the expense of poor DC load regulation. Conventional solutions use permanent or switched dummy loads to improve direct current (DC) load regulation and to prevent overshoots. Conventional solutions provide better control of output voltage over the load current range. One conventional solution uses fast voltage comparators to switch on/off dummy loads or additional current sourcing elements.
FIG. 1 illustrates a conventional replica type voltage regulator circuit in a schematic diagram designated by general reference character 100. The voltage regulator circuit 100 includes an operational amplifier (OPAMP) 101 comprising an n-type metal oxide silicon (NMOS) device 102 which forms the output stage of the OPAMP 101. The voltage regulator circuit 100 further comprises a triple well process scheme in which the bulk of the NMOS device 102 is coupled to its source terminal for improved output regulation. The source terminal of the NMOS device 102 is coupled to a feedback resistor 105 divider network to'form a loop node (Vpwr-loop) of the OPAMP 101. The tap point of the feedback resistor divider network 105 is further fed back to the input of the OPAMP 101 to form a closed loop path. The OPAMP 101 is coupled to an output transistor 103 that has a source terminal forming the output node (Vpwr) of the voltage regulator circuit 100. A load current source 104 coupled to the output node acts as an internal leakage path for the voltage regulator circuit 100. The OPMAP 101 is enabled with a reference voltage (VREF) that is compared with the closed loop to generate an NGATE output voltage that further provides a regulated voltage at the output node (Vpwr). The resistor divider network 105 and the load current source 104 together contribute to the tuning of the circuit to provide a regulated output voltage (Vpwr).
FIG. 2 illustrates another conventional replica type voltage regulator circuit in a schematic diagram designated by general reference character 200. The voltage regulator circuit 200 includes an OPAMP device 201, an NMOS device 202, an output transistor device 203, and a load current source 204. The voltage regulator circuit 200 is similar in structure and function as the voltage regulator circuit 100 illustrated in FIG. 1, except that the feedback resistor divider circuit is replaced by discrete elements to provide finer tuning of the regulator output voltage (Vpwr). The discrete elements are comprised of transistors and designated as 205, 206, 207, 208 and 209. Divider tap points tp1, tp2, tp3 and tp4 are formed between consecutive discrete elements (e.g., divider tap point tp1 is formed between discrete elements 205 and 206 divider tap point tp2 is formed between discrete elements 206 and 207, divider tap point tp3 is formed between discrete elements 207 and 208, and divider tap point tp4 is formed between discrete elements 208 and 209). The divider tap points tp1-tp4 are fed back in steps to the OPAMP 201 input (e.g., via feedback path “fdbk”).
Disadvantages of the conventional tuning methods illustrated in. FIGS. 1 and 2 include that the feedback resistor network must be continuous so that any fractional load variations can be achieved by sliding the tap point along the feedback network. A further disadvantage is that when the feedback resistor network is replaced by discrete elements, such as transistor devices, the step size of tuning is very high, thereby leading to course variations in the output voltage (Vpwr). Another disadvantage is that tuning the default load current source at the regulator output node consumes excessive power.